The present invention relates to data communications.
In high-speed serial links of data communications networks, losses in signal integrity occur as a data signal is communicated over a non-ideal channel such as a coaxial cable or a backplane between transmitter and receiver cards at respective ends of a link. As the data signal propagates through a non-ideal channel, it experiences losses due to non-ideal transmission line effects, as well as lumped parasitic elements that exist in the vias, connectors, package, etc. that occur along the channel and which effectively attenuate high frequency components, and thus, distort the signal. One result of the distortion is an increase in jitter. An effect of jitter is a decrease in the width of the eye opening of the data signal received by a receiver. A narrower eye opening makes individual data bits carried by the data signal less likely to be received correctly, while a wider eye opening makes the bits more likely to be received correctly. Thus, the eye opening of the received signal is highly correlated with bit error rate. Therefore, the eye opening is a figure of merit for the quality of the channel and the transmitter and receiver which communicate over the channel.
One of the challenges of a data communications system is to provide a system and method of automatically performing adaptive equalization capable of use with transmission channels having different coupling modes and nominal transmission frequencies.
Another challenge is to provide automatic adaptive equalization to counteract losses at higher frequencies, which are not known a priori, for example, when losses are due to the particular installation of the transmitter, receiver, and transmission channel between them.
In non-ideal transmission channels, the amplitude of a signal near the upper frequency limit of any of the transmitter, receiver, and transmission line is attenuated. The frequency characteristic tends to be spread over a broad range of frequencies, causing signal integrity to be degraded. This is felt particularly by integrated circuit chips and core elements of chips which have a serializer-de-serializer (SerDes) function, i.e. chips and subsystems of chips (collectively, “SerDes chips”) which perform high switching speed serial data transmission, reception or both. SerDes chips are typically interconnected via a backplane, one or more cables, or both backplane and cables. A goal of designing SerDes chips is to counteract attenuation at higher frequencies, and accordingly improve the integrity of signals transmitted over a non-ideal transmission channel.
Referring to FIG. 1, a conventional data transmitter is illustrated, in which parallel input data DIN0, DIN1, DIN2 and DIN3 are first serialized by a serializer 10, then passed to a N tap FFE 11. The output of the transmitter, serialized high-speed differential data signals TXDP and TXDN are terminated differentially with 100 Ohm impedance by a transmitter resistor termination circuit 13 to avoid reflections. The purpose of the Feed Forward Equalizer (FFE) 11 is to amplify higher frequency spectral content of the data being transmitted more than the spectral content at other frequencies. Another purpose is to counteract inter-symbol-interference (ISI). The degree to which the spectral content is amplified at different frequencies is controllable by the relative magnitudes and signs of the tap coefficients of the FFE 11.
In general, an FFE 11 includes a Finite Impulse Response (FIR) filter 11a, which is followed by a driver stage 11c. In the particular example shown in FIG. 1, an optional pre-driver stage 11b is coupled between the FIR filter 11a and the driver stage 11c. Typically, a FIR filter includes a shift register including a series of taps into which a stream of data bits including preceding, current and succeeding bits is loaded serially for transmission. The output of the FIR filter is generated as a weighted sum of the stream of data bits present in the shift register at any given point in time, the sum weighting individual data bits of the stream with tap coefficients. The weighted sum can be expressed as a transfer function between input and output of the FIR filter in the z domain having a form of typically H(z)=S[1+(b1)z−1+(b2)Z−2+(b3)z−3 . . . +(bn)z−n], where b1, b2 b3 and bn are the tap coefficients (the tap coefficients normally being set by registers in the logic). S is a scaling factor and all coefficients are negative for the purpose of pre-emphasis. The determining factors of the FIR filter coefficients include the characteristics of the transmission media, transmission data rate, type of board connector and package, etc.
Specifically, the N tap FFE 11 includes an N tap FIR 11a followed by N pre-drivers 11b and/or N drivers 11c in parallel. The FFE tap coefficients b0, b1, b2, and bn are biasing currents of the driver stage which are determined by control signals T0, T1, T2, and Tm, as presented to a digital to analog converter (DAC) 12. These control signals T0, T1, T2, and Tm are generated elsewhere by logic and provided to the DAC 12 through registers. In general, customers set the control signals T0, T1, T2, and Tm for the FFE tap coefficients to vendor-recommended values through such registers according to the needs of their particular application.
A conventional data receiver for receiving signals such as the type transmitted by the transmitter 100 is illustrated in FIG. 2. As illustrated, serialized high-speed differential data signals RXDP and RXDN, arriving from a transmission channel (not shown), are terminated differentially with 100 Ohm impedance by a receiver resistor termination circuit 23 to reduce reflections. A receiver common mode voltage bias circuit 24 is used to allow optimal data receiver common mode voltage selection for different operation modes (AC-coupled mode or DC-coupled mode). Serialized data RXDP and RXDN are received at the data receiver front circuitry 20 and then deserialized back to parallel format by the de-serializer 21. In general, a signal detect circuit 22 is required as part of the data receiver to have the capability of detecting whether there is a valid incoming data at front of the data receiver.
In practice, as an initial step to placing SerDes chips in use, several different lengths of cable and/or interconnects of a backplane are characterized to determine optimal FFE settings for the data transmitter 100 that result in minimum jitter. Customers are then given information for setting the tap coefficients of the FFE. Settings for the tap coefficients can then be entered through a register interface.
When a SerDes chip is operated, the transmitted data eye of the output at a given point within the system can be optimized by manually manipulating the control settings including the tap coefficient settings, and observing the results on an oscilloscope. The control settings are then applied to all of the SerDes units used in the same way, i.e. all SerDes units installed for use in a particular application to operate at a particular speed, having particular transmission parameters, etc.
The above-described techniques for determining appropriate control settings generally involve an “equalization” function that can be described as “preset” equalization, the equalization being a degree to which particular frequencies of the transmission signal are emphasized. Preset equalization requires settings to be determined separately for each particular application in which the SerDes units are installed. For that reason, preset equalization is considered to be an inflexible approach to determining control settings. However, preset equalization may result in the settings for some SerDes units being incorrectly set, leading to problems. If less than enough equalization is applied, compensation for high frequency loss will not be very effective. On the other hand, if too much equalization is applied, excessive power is consumed, and excessive cross-talk noise could be generated and presented to links which carry signals from neighboring SerDes units.
There are various existing equalization circuits such as FFE (Feed Forward Equalizer) discussed above, DFE (Decision Feedback Equalizer), and other built-in pre-distortion circuits to compensate high frequency attenuation due to non-ideal transmission channels. However, they are either data transmitter based or data receiver based. In other words, no feedback or any communication is established between data transmitter and data receiver. None of them is able to fully analyze the transmission channel characteristics and then accordingly calibrate the equalization parameters. None of them can optimally compensate high frequency loss due to the transmission channel.
U.S. Pat. No. 6,563,863 (the '863 patent”) describes an echo cancellation scheme used in a modem of a computer having a central processing unit (CPU). The computer modem has a transceiver interface, which includes a digital-to-analog converter (data transmitter) and an analog-to-digital converter (data receiver) for converting samples to/from analog signals for transmission on a telephone line (transmission channel). Two conventional adaptive FIR (Finite Impulse Response) filters are used. The first filter is used to adapt in response to an echo correlation between data transmitted over a transmit channel of the modem and data received on a receive channel of the transceiver interface during normal operation. The second filter, referred to in the '863 patent as an echo canceller, adapts in response to the echo estimated by the first filter during period in which the first filter is “starved” of data. The echo canceller is then used to subtract the adapted echo from the received signal to obtain only the far modem signal during normal operation. A closed loop feedback path is established between the transmitter and receiver to adaptively adjust two FIR filters in response to the changing echo characteristics of transmission path. However, in the '863 patent, the closed loop feedback path is through the interface to the CPU, instead of through a transceiver interface.